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特聘講座/特聘研究員   ｜   Distinguished Chair and Distinguished Research Fellows








              EDUCATION:                                             versity	of	Minnesota,	Minneapolis,	MN.	(1994-present)
 游本中 Pen-Chung Yew  	 ● Ph.D.,	Computer	Science,	University	of	Illinois,	Urbana,	Illinois	(1981)
               	 ● M.S.,	Electrical	and	Computer	Engineering,	University	of	Massachu-  ACADEMIC HONORS AND AWARDS:
                setts,	Amherst,	Massachusetts	(1977)               	 ƒ IEEE	Fellow
               	 ● B.S.,	Electrical	Engineering,	National	Taiwan	University,	Taipei,	Taiwan	  	 ƒ EMC	Visiting	Chair	Professor,	Tsinghhua	University,	Beijing,	PRC
 特聘研究員 Distinguished Research Fellow  (1972)                         (2008-2010)
 美國伊利諾大學資訊科學系博士  PROFESSIONAL EXPERIENCE:                          	 ƒ William	Norris	Land-Grant	Chair	Professor,	University	of	Minnesota
               	 ● Distinguished	Research	Fellow,	Institute	of	Information	Science,	  (2000-2005)
 Tel:	+886-2-2788-3799	ext.	2202  Academia	Sinica,	(2008-present)  	 ƒ IEEE	Computer	Society	Meritorious	Award	(2005)
 Fax:	+886-2-2782-4814  	 ● Head,	Department	of	Computer	Science	and	Engineering,	University	  EDITORIALSHIPS:
 Email:	yew@iis.sinica.edu.tw  of	Minnesota,	Minneapolis,	MN	(2000-2005)  	 ƒ Editor-in-Chief,	IEEE	Transactions	on	Parallel	and	Distributed	Systems
 http://www.iis.sinica.edu.tw/~yew/  	 ● Professor,	Department	of	Computer	Science	and	Engineering,	Uni-  (2002-2005)





              代表著作 Publications


              1.   Z. Wang, C. Wu and P.C. Yew, “On Improving Heap Memory Layout   actions on Architecture and Code Optimization, Vol.1, No.3, Septem-
                 by Dynamic Pool Allocation,” Proc. of the 8^th Annual IEEE/ACM   ber 2004, pp. 247-271
 研究簡介  Research Description  Int’l  Symp.  on  Code  Generation  and  Optimization  (CGO),  April,   16.  J. Lu, H. Chen, R. Fu, W.C. Hsu, B. Othmer and P.C. Yew, The Per-
                 2010.
                                                                      formance of Runtime Data Cache Prefetching in a Dynamic Optimi-
 目前我主要研究方向是在發展新一代高性能及低功耗率  My	main	research	effort	involves	the	design	of	future	generations	of	high-perform-  2.   L. Wang, et. al., “An Adaptive Task Creation Strategy for Work-Steal-  zation System, Proc. of 36th Annual Int’l Symp. on Microarchitecture
 的電腦系統，包括微處理機及多處理機	(multiprocessor   ance	and	low-power	computer	systems,	including	both	microprocessors	and	multi-  ing Scheduling,” Proc. of the 8^th Annual IEEE/ACM Int’l Symp. on   (MICRO-36), December 2003
                 Code Generation and Optimization (CGO), April, 2010.
 )	 系統。主要的研究重點在於體系結構	 (architectures)  processors.	I	am	interested	in	issues	related	to	their	machine	architectures,	program-  17.  H.B. Lim and P.C. Yew, Efficient Integration of Compiler-Directed
 、程式模式	 (programming	 models)、編譯系統和系統  ming	models,	compilation	techniques	and	system	software.	  3.   H. Chen, L. Yuan, X. Wu, B. Zang, B. Huang, P.C. Yew, “Control   Cache Coherence and Data Prefetching, Journal of Parallel and Dis-
                                                                      tributed Computing, Vol. 61, No. 12, Dec 2001, pp. 1775-1802
                 Flow Obfuscaton with Information Flow Tracking,” Proc. of the 42nd
 軟件。             Int’l Symp. on Microarchitecture (MICRO-42), November 2009.
 In	the	design	of	future	generations	of	microprocessors,	we	focus	on	multi-threaded,	  18.  S.Y.Cho, P.C. Yew and G. Lee, A High-Bandwidth Memeory Pipeline
 在微處理機方面，著重於多線	 (multi-threads)	 及多核  multi-core	architectures	that	exploit	both	thread-level	and	instruction-level	parallel-  4.   V. Packirisamy, A. Zhai, W.C. Hsu, P.C. Yew, T.F. Ngai, “Exploring   for Wide-Issue Processors, IEEE Trans. on Computers, Vol. 50, No.7
 的體系統結構設計，尤其是利用指令級程	(instruction-  ism,	possibly	with	speculation	support,	to	achieve	high	performance	with	reduced	  Speculative Parallelism in SPEC2008,” Proc. of Intn’l Symp. On Per-  , July 2001, pp. 709-723.
                 formance Analysis of Systems and Software (ISPASS), April 2009.
 level)	及執行線級程	(thread-level)	的並行性來提高系統  power	consumption.	The	targeted	systems	range	from	large-scale	parallel	machines	  19.  L.Choi and P.C. Yew, Hardware and Compiler-Directed Cache Co-
 的性能並降低其功率的損耗。並期望進一步地將上述的  to	application-specific	embedded	systems.	  5.   V. Packirisamy, A. Zhai, W.C. Hsu, P.C. Yew, T.F. Ngai, Exploring   herence in Large-Scale Multiprocessors, the IEEE Trans. on Parallel
 研究成果，運用至大型平行處理機以及小型特殊用途的  Our	 compiler	 effort	 is	 centered	 on	 a	 profile-based	 approach	 that	 supports	 both	  Speculative Parallelism in SPEC2008, Proc. of Int’l Symp. On Per-  and Distributed Systems, Vol. 11, No. 4, April 2000, pp. 375-394.
                 formance Analysis of Systems and Software (ISPASS), April 2009.
 嵌入式處理機。                                                          20.  I.H. Kazi, et al., JaViz: A Client/Server Java Profiling Tool, a special
 medium-grained	(loop	iteration-level)	and	fine-grained	(instruction-level)	parallel-  6.   Y. Duan, X. Feng, P.C. Yew, “Detecting and Eliminating Potential Vi-  issue on Java technology in IBM Systems Journal, Vol. 39, No.1.1,
 有關編譯系統的研究，是利用在執行期間的採樣方法   ism	with	speculation,	low	power,	and	latency	hiding	schemes.	In	this	research	area,	  olation of Sequential Consistency for Concurrent C/C++ Programs,”   2000.
 (profiling)去發掘中粒度	 (medium-grained)	 及細粒度   we	investigate	both	static	(at	compile	time)	and	dynamic	(at	runtime)	compilation	  Proc. of the 7^th Annual IEEE/ACM Int’l Symp. on Code Generation   21.  J.Y.Tsai,  et  al.,  The  Superthreaded Architecture,  a  special  issue  on
 (fine-grained)	 的平行性，並利用”投機”	 (speculation)	  techniques.	We	also	study	binary	translation	techniques	that	support	cross-platform	  and Optimization (CGO), March 2009.  multithreaded architectures in the IEEE Trans. on Computers, Vol 48,
 的方式去挖掘執行程式中更多的平行性，同時希望編譯  execution.	New	parallel	programming	models	that	support	specific	applications	of	  7.   P. Woodward, J. Jayaraj, P.H. Lin, P.C. Yew, Moving Scientific Codes   No. 9, September 1999, pp. 881-903.
 產生出的程式更能減低執行時的功耗及減少存儲器存取  domain	experts	are	another	area	of	interest.	  to IBM Cell Processor and Other Multicore Microprocessor CPUs,   22.  D.K. Chen and P.C. Yew, Redundant Synchronization Elimination for
                 IEEE Computing in Science and Engineering, Nov 2008
 資料時浪費的時間。我們發展的編譯技術範圍包括一般  In	system	software	research,	we	currently	focus	on	operating	system	support	for	  Doacross Loops, IEEE Trans. on Parallel and Distributed Systems,
 的靜態編譯	(static	compilation)	技術，與執行期間的動  multi-core	embedded	systems,	and	on	supporting	virtualization	for	various	applica-  8.   V. Packirisamy, Y. Luo, W.L. Hung, A. Zhai and P.C. Yew, Efficiency   Vol.10, No. 5, May 1999.
                 of Thread-Level Speculation in SMT and CMP Architectures – Per-
 態編譯	(dynamic	compilation)	技術。為了讓編譯器能產  tions  formance, Power and Thermal Perspective, Proc. Of Int’l Conf. on   23.  H.B.Lim and P.C. Yew, Maintaining Cache Coherence Through Com-
 生更高效能的執行程式，我們也研究新的程式編寫模式   Computer Design (ICCD), Oct. 2008.        piler-Directed Data Prefetching, Journal of Parallel and Distributed
                                                                      Computing, Vol 53, No. 2, pp. 144-173, Sep 1998.
 (programing	models)	讓專門學科的非電腦專家能更容易  We	adopt	an	experimental	approach	to	the	above	design	issues,	with	on-going	de-  9.   H. Chen, X. Wu, L. Yuan, B. Zang, P.C. Yew, F.T. Chong, From Spec-
 的編寫他們領域所需的應用軟件。  velopment	of	compiler	and	architectural	simulation	infrastructures	to	support	our	  ulation Security: Practical and Efficient Information Flow Tracking   24.  J.Y.Tsai, P.C. Yew, et al, Integrating Parallelizing Compilation Tech-
                                                                      nology  and  Processor  Architecture  for  Cost-Effective  Concurrent
 research	efforts.  Using Speculative Hardware, Proc. of 35th Int’l Symp. on Computer
 系統軟件的研究主要是發展多核嵌入系統的操作系統，  Architecture (ISCA-35), June 2008          Multithreading, a special issue in Journal of Information Science and
 並支持系統的虛擬化，以提高機器和軟件的可用性及可  10.  S.V. Kodakara, J. Kim, D.J. Lilja, D. Hawkins, W.C. Hsu, and P.C.   Eng, No. 14, pp.205-222, March 1998
 靠性。             Yew, CIM: A Reliable Metric for Evaluating Program Phase Clas-
                 sifications, IEEE Computer Architecture Newsletter, 2007
 我們的研究方法是採用實做的方式去編寫大型編譯器，
 並發展高性能模擬器以測量驗證發展出來的新體系結  11.  J.Kim, W.C. Hsu and P.C. Yew, COBRA: An Adaptive Runtime Bi-
 構、編譯技術、系統及應用軟件的功能並發掘新的問題  nary Optimization Framework for Multithreaded Applications, Proc.
                 of Int’l Conf. on Parallel Processing (ICPP), Sept. 2007
 以做更深入的研究。
              12.  H.Chen, J.Yu, C.Rong, B.Y.Zang and P.C.Yew, POLUS: A Powerful
                 Live Updating Systems, Proc. of Int’l Conf. on Software Engineering
                 (ICSE), May, 2007
              13.  J.Lin, W.C. Hsu, P.C. Yew, R.D.C. Ju, and T.F. Ngai, Recovery Code
                 Generation  for  General  Speculative  Optimizations, ACM  Transac-
                 tions  on Architecture  and  Code  Optimization,  Vol.3,  No.1,  March
                 2006, pp. 67-89
              14.  X. Dai, A. Zhai, W.C. Hsu and P.C. Yew, A General Compiler Frame-
                 work  for  Speculative  Optimizations  Using  Data  Speculative  Code
                 Motion, Proc. of the Third Annual IEEE/ACM Int’l Symp. on Code
                 Generation and Optimization (CGO), March 2005, pp. 280-290
              15.  J.Lin, T.Chen, W.C. Hsu, P.C. Yew, R.D.C. Ju, T.F. Ngai and S. Chan,
                 A Compiler Framework for Speculative Optimizations, ACM Trans-

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