Institute of Information Science Academia Sinica
Topic: Efficient Dynamic Binary Translation and Optimization
Speaker: Dr. Ding-Yonlg Hong (Institute of Information Science, Academia Sinica)
Date: 2020-03-31 (Tue) 10:00 – 12:00
Location: Auditorium106 at IIS new Building
Host: Meng-Chang Chen


Dynamic binary translation (DBT) is the core technology to many important applications, such as full system virtualization, binary instrumentation, security monitoring, HW/SW verification, and application migration to new architectures. There are several factors that often impede the DBT performance: (a) emulation overhead before translation; (b) translation and optimization overhead; and (c) translated code quality. The issues also include its retargetability that supports translations across many different ISAs—an important feature to system virtualization. In this talk, I will introduce HQEMU (Hybrid-QEMU), an efficient and retargetable dynamic binary translator on multicores. We propose to use QEMU as HQEMU’s frontend emulator, and leverage the LLVM optimizing compiler as its backend to dynamically optimize code for higher performance. With the hybrid QEMU LLVM approach, we successfully address the dual issues of high-quality translated code and low translation overhead,achieving more than 25x speedup over the state-of-the-art QEMU system. Based on HQEMU, we designed several dynamic parallelization and optimization tools. This talk will also present our binary re-vectorization tool, which can transform short-SIMD binaries to long-SIMD codes. The proposed binary re-vectorizer allows legacy applications to achieve greater SIMD parallelism when running such short-SIMD application binaries on newer architectures with longer SIMD lanes. Finally, I will present how to design a dynamic binary optimizer that can enhance transactional memory execution.


Ding-Yong Hong received the Ph.D. degree in Computer Science from National Tsing Hua University, Taiwan, in 2013. He is currently a postdoctoral research fellow and a senior software engineer in the Institute of Information Science, Academia Sinica. His research results have been published in the international journals such as IEEE TPDS, ACM TACO, and ACM TECS, and in the top-rated conferences including IEEE/ACM CGO, ACM PACT, IEEE ICPADS, and IEEE ICPP. His work received the Best Paper Award from IEEE ICPADS 2016 (out of 412 submissions), and the work published in ACM PACT is the first Taiwan paper accepted by PACT since its establishment in 26 years. He was invited for a talk to share the design experience and solutions of the HQEMU dynamic binary translator at Intel US, Google US, and the HiPEAC 2016 and 2019 conference (European Network of Excellence on High Performance and Embedded Architecture and Compilation). His research interests include the areas of compilers and computer architectures. His current research focuses on (1) AI compiler, optimizing compiler, and dynamic binary translation; (2) parallel computing and parallel architectures, including multicores, GPU, GPGPU, MIC, and SIMD acceleration; (3) virtualization.